Flip chip packaging techniques have become more widely used in the semiconductor packaging field. The flip chip technique allows use of the entire active face of a semiconductor integrated circuit (IC) die for interconnections to the package substrate. This increases the density of pins relative to wire bonding. However, the density of contacts which can be formed on the package substrate has not increased as quickly as the density of the pads of the IC. Thus, the minimum pitch between contacts on the package substrate is greater than the minimum pitch between pads on the IC die.
The fan-out wafer form (also called a “reconfigured wafer”) provides a solution to this problem. In this method, a wafer containing a plurality of IC dies is processed, tested, grinded and singulated. The active faces of the dies are arranged in a spaced out fashion on a release tape over a carrier substrate. The back face and side edges of the dice are encapsulated in a molding compound. The compound is cured. Then the carrier and release tape are removed. The resulting reconfigured wafer has dies with lanes of molding compound between the rows and columns of dies. The active face of the reconfigured wafer is also planar.
A redistribution layer is formed over the active face, partly overlying the dice and partly overlying the lanes of compound between the dice. The redistribution layer comprises a patternable dielectric material. Fan-out lines and vias are formed in the redistribution layer using photolithographic techniques. The top surface of the redistribution layer has a plurality of pads corresponding to the pads of the IC dies. The spacing between the pads at the top surface of the redistribution layer can thus be greater than the spacing on the active face of the die, so that some the pads of the redistribution layer are outside of the die area. Solder bumps are placed on the pads of the redistribution layer. The reconfigured wafer is then singulated, and the dies are connected to respective package substrates having a pad density lower than the pin density of the IC die.